While operating computer equipment, such as personal computers or computer servers, to provide Internet access, users would encounter system errors displayed as a general error message on the monitor of the computer system. These system errors could arise for any number of reasons, from computer program errors, from computer program conflicts with the computer components such as the microprocessor and the memory, or from a hardware error. Thus, a user that calls for service can only relay the information the computer gives them to a service technician. But to efficiently service a computer, the service typically needs additional information, such as circuit state information, and has had to go on-site to retrieve this information.
This circuit state information can be retrieved through test circuitry put in place for testing and component debugging purposes. A component circuit board may contain numerous integrated circuits (also known as "chips") having input/output ("I/O") pins for interconnecting various internal circuits of the chips. With the continual miniaturization of integrated circuitry, the number of pins have steadily increased. Testing of these interconnections and the associated I/O pins is a vital step in the design and manufacture of such circuit boards and chips.
One of the standards that has been implemented within the industry is JTAG (Joint Test Action Group) testing of an IEEE (Institute of Electrical & Electronics Engineers) 1149.1 standard-compliant device. The IEEE standard 1149.1 is described in detail in the IEEE Standard Test Access Port and Boundary-Scan Architecture.
The IEEE standard 1149.1 was developed to address the need to test components that were advancing in complexity, density, and packaging of semiconductor components. As a result, increased pin counts, reduced pin spacing, and inaccessible circuit nets had caused a general inability to apply common testing methods to verify proper operation of these components. In general, interconnect faults in chips, such as open circuits or short circuits, typically accounted for 75% or more of the manufacturing defects. There are many causes of opens and shorts: bent pins, excessive solder, insufficient solder, component misalignment, and others. The IEEE standard 1149.1 standard was formulated to provide a structured interconnect test and access method.
The IEEE standard 1149.1 consists of a 4-wire (optionally 5-wire) serial test bus with a standard protocol and a structured test technique called boundary scan. Boundary scan logic placed at the I/O pins of a component allows each pin to be controlled or observed for interconnect tests.
A ring architecture is provided by the IEEE 1149.1 architecture, which allows a simple interconnect and low gate count implementation of single board/card designs. Through this ring architecture, the IEEE standard 1149.1 had provided verification of functionality and correct interconnection of both compliant and non-compliant devices in a printed circuit board design, such as a computer motherboard. Under JTAG, testing was able to be performed without the presence of firmware by accessing the Test Access Port ("TAP"), and manipulating the process to imitate most of the bus signals for the board.
Apart from it original purpose of manufacturing defects testing, the IEEE standard 1149.1 had been used to provide a gateway to other capabilities such as design debug and validation, internal IC test, on-chip emulation, performance monitor logic, and system test features. Also, the IEEE standard 1149.1 had been used to access and control on-chip performance monitor and on-chip emulation logic.
Nevertheless, such test structures have not been available for on-demand access, either remotely or locally, so that a service technician can efficiently service the computer system.
Thus, a need exists for an apparatus and method for remote retrieval of circuit state information. A further need exists for an automated dial-in to a remote service center upon the occurrence of a computer system fault.